1. Field of the Invention
The present invention relates to infrared detector hybrid arrays. More particularly, the present invention relates to infrared detector hybrid arrays including an infrared detector array mounted on a silicon readout circuit.
2. Description of the Prior Art and Related Information
Space based infrared detection systems are of significant technological importance for both military and civilian space based monitoring applications. High performance infrared detection systems, typically referred to as infrared focal plane arrays, employ an infrared detector array mounted on a readout circuit. The detector array may typically employ a thin layered detector material, chosen adapted for the infrared frequency range to be monitored, formed monolithically on a suitable substrate transparent to infrared radiation in the frequency range desired. An array of photodiodes is formed in the thin layer of detector material. This detector array is then directly mounted on a readout circuit which is typically a conventional silicon integrated circuit having the necessary circuitry for picking up the signals detected by the detector array, amplifying them and processing them for the specific monitoring application.
Referring to FIG. 1, a conventional prior art hybrid infrared detector array is illustrated in cross-section. The conventional hybrid array includes a monolithic detector array 1 which includes, for example, a cadmium-telluride (CdTe) substrate 2 with a relatively thin active infrared detection layer 3 of HgCdTe on one major surface thereof. The infrared detector array 1 is "bump-bonded" to a readout circuit 4. The readout circuit 4 will typically be manufactured using conventional integrated circuit semiconductor processing technology and will thus have a silicon substrate 5 with the desired readout circuit formed on the upper surface 6 thereof. The conventional "bump-bonding" technique employs indium interconnects 7. These indium bumps 7, provide both the electrical interconnects between the infrared detector array 1 and the silicon readout circuit 4, as well as providing bonding between the detector array 1 and readout circuit 4. An epoxy bonding material (not shown) is also commonly employed to further bond the detector array 1 and readout circuit 4.
The indium bump bonded hybrid detector array, such as illustrated in FIG. 1, has the advantage that relatively large two-dimensional arrays may be fabricated. Additionally, the indium bump bonding technique provides low resistance and low capacitance interconnection between the detector 1 and the readout circuit 4.
One significant disadvantage of the prior art infrared detector array of FIG. 1, however, is the lack of reliability introduced by virtue of the difference in the temperature coefficient of thermal expansion between the detector array 1 and the readout circuit 4. More specifically, the hybrids are manufactured at room temperature under zero stress but operated at very low temperatures, typically less than 100.degree. K. As a result, considerable stress is introduced at the junction of the detector 1 and the readout circuit 4 due to the thermal mismatch. The significance of this problem may be appreciated by comparing the coefficients of expansion of various materials potentially involved in such hybrids through the temperature range of 30.degree.-300.degree. K., as illustrated in FIG. 2. As will be appreciated from FIG. 2, a significant difference in the coefficient of expansion exists between silicon, HgTe and CdTe throughout most of this temperature range.
In practice, the thermal mismatch problem manifests itself as either physical damage in the hybrid array or degraded performance. The physical damage may manifest itself as either local or global delamination of the hybrid, i.e., actual separation of the indium bumps between the detector and readout circuit, or cracking of the detector array. The performance degradation may manifest itself as lack of uniformity between arrays, within an array, or as a general reduction in performance specifications. Additionally, the magnitude of the thermal mismatch problem is directly proportional to the size of the array. For example, for arrays of one inch by one inch, more than 17 microns of mismatch exists between the silicon readout circuit and a HgCdTe detector array after cooling from room temperature to a cryogenic temperature of about 77.degree. K. As a result, in practice the size of hybrid arrays have been limited to about 0.25 inches by 0.25 inches by the thermal mismatch and associated reliability problems. This limitation in size has occurred despite the key advantage of large arrays for infrared detection sensitivity and spatial resolution capability.
Several attempts have been employed in the prior art to attempt to overcome the thermal mismatch problem and allow increased size detector arrays. One such approach has been to employ taller indium bumps 7, the taller bumps allowing some lateral bending of the bumps to accommodate the thermal mismatch before delamination or cracking occurs. Although this approach can provide some reduction in the thermal mismatch problem for smaller arrays, it is inherently limited in its application to larger arrays, for example, much greater than about 0.3 inches by 0.2 inches. Also, where the hybrid array is required to be back filled with epoxy to provide adequate bonding between the detector array and the readout circuit, the use of taller indium bumps is not a viable solution. This will typically limit the use of indium bump bonding with taller columns to applications where an epitaxial detector layer, such as HgCdTe is formed on a detector substrate such as CdTe. Furthermore, such approach has not proven to be viable in applications requiring long term reliability, having multiple thermal cycles, and/or high G force environments.
In another approach, the thermal mismatch problem has been reduced somewhat by the deletion of the epoxy used to bond the detector array and silicon readout circuit together. In particular, some improvement is provided when this is combined with taller indium bumps to allow the bumps to flex somewhat to accommodate the thermal mismatch. Although this approach may be suitable for laboratory demonstrations of hybrid arrays, since the epoxy is not present to strengthen the bond between the array and readout circuit, the resultant hybrid is quite susceptible to delamination since only the indium bonds provide the bonding. Therefore, the stress introduced during handling and assembly, and in space based applications, where high G forces and/or high vibration will be present, makes this approach unsuitable in practice.
Another approach to the thermal mismatch problem has been to employ a substrate which has a closer thermal coefficient of expansion to silicon as the substrate for the infrared detector active layer. For example, sapphire has been employed as a substrate for HgCdTe epitaxial detector layers to provide an improved thermal match with the silicon readout circuit. As may be appreciated from FIG. 2, sapphire has a much closer coefficient of expansion to silicon than does CdTe, the more common detector substrate. Nonetheless, some mismatch in the coefficient of expansion does exist between sapphire and silicon, leading to at most a reduction, not an elimination of the thermal mismatch problem. Also, the use of a sapphire substrate for the detector array has resulted in reduced detection performance levels. As a result, the use of alternate substrates for the detector array has not proven to be an adequate solution to the thermal mismatch problem.
Accordingly, none of the existing approaches to reducing or eliminating the thermal mismatch problem are suitable for solving the problem in applications involving desired large arrays in applications such as space based monitoring where large G forces and high vibration will be present. Accordingly, a need presently exists to provide a solution to the thermal mismatch problem in a manner which is practical for such desired applications.